2 megabit high speed cmos sram dps128x16cn3/dps128x16bn3 description: the dps128x16cn3/dps128x16bn3 high speed sram ??stack?? modules are a revolutionary new memory subsystem using dense-pac microsystems? ceramic stackable leadless chip carriers (slcc). available in straight leaded, ??j?? leaded or gullwing leaded packages, or mounted on a 50-pin pga co-fired ceramic substrate. the module packs 2-megabits of low-power cmos static ram in an area as small as 0.463 in 2 , while maintaining a total height as low as 0.171 inches. the dps128x16cn3/dps128x16bn3 stack modules contain two individual 128k x 8 srams, each packaged in a hermetically sealed slcc, making the modules suitable for commercial, industrial and military applications. the dps128x16bn3 has one active low chip enable ( ce ) and while the dps128x16cn3 an active low chip enable ( ce ) and an active high select line (sel). by using slccs, the ??stack?? family of modules offer a higher board density of memory than available with conventional through-hole, surface mount or hybrid techniques. features: organizations available: 128kx16 or 256kx8 access times: 20, 25, 30, 35, 45ns fully static operation - no clock or refresh required single +5v power supply, 10% tolerance ttl compatible common data inputs and outputs low data retention voltage: 2.0v min. packages available: 48 - pin slcc stack 48 - pin straight leaded stack 48 - pin ??j?? leaded stack 48 - pin gullwing leaded stack 50 - pin pga dense-stack 256kx8/128kx16, 20 - 45ns, stack/pga 30a097-32 e slcc stack straight leaded stack ??j?? leaded stack gullwing leaded stack dense-stack this document contains information on a product that is currently released to production at dense-pac microsystems, inc. dense-pac reserves the right to change products or specifications herein without prior notice. 30a097-32 rev. g 1
dps128x16cn3/dps128x16bn3 dense-pac microsystems, inc. pin-out diagram pin names a0 - a16 address inputs i/o0 - i/o15 data input/output ce 0, ce 1 low chip enables sel0, sel1 high chip enables we write enable oe output enable v dd power (+5v) v ss ground n.c. no connect note: sel0 and sel1 apply to dps128x16cn3 version only, no connect for dps128x16bn3 version. functional block diagram note: sel0 and sel1 apply to dps128x16cn3 version only. 48 - pin leadless stack 48 - pin straight leaded stack 48 - pin ??j?? leaded stack 48 - pin gullwing leaded stack 50 - pin pga dense-stack 30a097-32 rev. g 2
dense-pac microsystems, inc. dps128x16cn3/dps128x16bn3 recommended operating range 3 symbol characteristic min. typ. max. unit v dd supply voltage 4.5 5.0 5.5 v v ih input high voltage 2.2 v dd +0.3 v v il input low voltage -0.5 2 0.8 v t a operating temperature m/b -55 +25 +125 o c i -40 +25 +85 c 0 +25 +70 truth table mode sel ce we oe i/o pin supply current not selected l x x x high-z standby not selected x h x x high-z standby d out disable h l h h high-z active read h l h l d out active write h l l x d in active h = high l = low x = don?t care note: sel applies to dps128x16cn3 version only. dc output characteristics symbol parameter conditions min. max. unit v oh high voltage i oh = -4.0ma 2.4 v v ol low voltage i ol =8.0ma 0.4 v absolute maximum ratings 3 symbol parameter value unit t stc storage temperature -65 to +150 c t bias temperature under bias -55 to +125 c v dd supply voltage 1 -0.5 to +7.0 c v i/o input/output voltage 1 -0.5 to v dd +0.5 v dc operating characteristics: over operating ranges symbol characteristics test conditions typ. (?) c i m unit min. max. min. max. min. max. i in input leakage current v in = 0v to v dd - -10 +10 -10 +10 -10 +10 m a i out output leakage current v i/o = 0v to v dd , ce or oe = v ih , or we = v il - -10 +10 -10 +10 -10 +10 m a i cc operating supply current cycle=min., duty=100% i out = 0ma x8 125 180 190 210 ma x16 200 280 280 320 i sb1 full standby supply current v in 3 v dd -0.2v or v in v ss +0.2v 0.8 10 10 20 ma i sb2 standby current (ttl) ce = v ih 50 80 100 100 ma i dr3 data retention supply current (3.0v) v dr = 3.0v, ce 3 v dr -0.2v, (or sel 0.2v, v in 3 v dd -0.2v or v in +0.2v) 140 800 1200 4600 m a i dr2 data retention supply current (2.0v) v dr = 2.0v, ce 3 v dr -0.2v, (or sel 0.2v, v in 3 v dd -0.2v or v in +0.2v) 70 500 800 3600 m a v ol output low voltage i out = 8.0ma - 0.4 0.4 0.4 v v oh output high voltage i out = -4.0ma - 2.4 2.4 2.4 v ? typical measurements made at +25 o c, cycle = min., v dd = 5.0v. note: test conditions in parenthesis apply to dps128x16cn3 version only. capacitance 4 : t a = 25c, f = 1.0mhz symbol parameter max. unit condition c adr address input 25 pf v in 2 = 0v c ce chip enable 25 c sel active high chip select 25 c we write enable 30 c oe output enable 25 c i/o data input/output 20 note: c sel applies to dps128x16cn3 version only. 30a097-32 rev. g 3
dps128x16cn3/dps128x16bn3 dense-pac microsystems, inc. data retention waveform: sel controlled. (applies to dps128x16cn3 only) data retention waveform: ce controlled. v dd 4.5v sel v dr2 0.4v 0v sel -0.2v v dd 4.5v 2.3v v dr1 ce 0v ce 3 v dd -0.2v +5v 255 w 480 w c l * d out figure 1. output load * including probe and jig capacitance. output load load c l parameters measured 1 100pf except t lz1 , t lz2 , t hz1 , t hz2 , t ohz , t olz , and t whz 2 5pf t lz1 , t lz2 , t hz1 , t hz2 , t ohz , t olz , and t whz note: t lz2 and t hz2 apply to dps128x16cn3 version only. ac test conditions input pulse levels 0v to 3.0v input pulse rise and fall times 5ns input and output timing reference levels 1.5v data retention ac characteristics 8 symbol parameter test conditions min. typ. max. unit v dr v dd for data retention ce 3 v dr -0.2v, (sel 3 v dr -0.2v, or v in v dr -0.2v or v in 0.2v) 2.0 - - v v cdr chip disable to data retention time see data retention waveform 0 - - ns t r operation recovery time see data retention waveform 5 - - ms note: test conditions in parenthesis apply to dps128x16cn3 version only. 30a097-32 rev. g 4
dense-pac microsystems, inc. dps128x16cn3/dps128x16bn3 read cycle note: sel, t co2 , t lz2 and t hz2 apply to dps128x16cn3 version only. address ce sel oe data i/o waveform key data valid transition from transition from data undefined high to low low to high or don?t care ac operating conditions and characteristics - read cycle: over operating ranges no. symbol parameter 20ns 25ns 30ns 35ns 45ns unit min. max. min. max. min. max. min. max. min. max. 1 t rc read cycle time 20 25 30 35 45 ns 2 t aa address access time 20 25 30 35 45 ns 3 t co1 ce to output valid 20 25 30 35 45 ns 4 t co2 sel to output valid 20 25 30 35 45 ns 5 t oe output enable to output valid 8 10 15 20 25 ns 6 t lz1 ce to output in low-z 4, 5 3 3 3 3 3 ns 7 t lz2 sel to output in low-z 4, 5 3 3 3 3 3 ns 8 t olz output enable to output in low-z 4, 5 0 0 0 0 0 ns 9 t hz1 ce to output in high-z 4, 5 10 12 15 20 25 ns 10 t hz2 sel to output in high-z 4, 5 10 12 15 20 25 ns 11 t ohz output enable to output in high-z 4, 5 8 10 15 20 25 ns 12 t oh output hold from address change 3 3 3 3 3 ns note: t co2 , t lz2 and t hz2 apply to dps128x16cn3 version only. 30a097-32 rev. g 5
dps128x16cn3/dps128x16bn3 dense-pac microsystems, inc. ac operating conditions and characteristics - write cycle 6, 7 : over operating ranges no. symbol parameter 20ns 25ns 30ns 35ns 45ns unit min. max. min. max. min. max. min. max. min. max. 13 t wc write cycle time 20 25 30 35 45 ns 14 t aw address valid to end of write 15 20 25 30 40 ns 15 t cw chip enable to end of write 15 20 25 30 40 ns 16 t as address set-up time * 0 0 0 0 0 ns 17 t wp write pulse width 15 20 25 30 35 ns 18 t wr write recovery time 0 0 0 0 0 ns 19 t whz write enable to output in high-z 4, 5 8 10 12 15 20 ns 20 t dw data to write time overlap 12 15 15 20 25 ns 21 t dh data hold from write time 0 0 0 0 0 ns 22 t ow output active from end of write 3 3 3 3 3 ns * valid for both read and write cycles. write cycle 1: ce controlled. 8 address ce we data in data out notes: 1. all voltages are with respect to v ss . 2. -2.0v min. for pulse width less than 20ns (v il min. = -0.5v at dc level). 3. stresses greater than those under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 4. this parameter is guaranteed and not 100% tested. 5. transition is measured at the point of 500mv from steady state voltage. 6. when oe and ce are low and we is high, i/o pins are in the output state,and input signals of opposite phase to the outputs must not be applied. 7. the outputs are in a high impedance state when we is low. 8. sel timing is the same as ce timing (valid for dps128x16cn3 only). the waveform is inverted. 9. chip enable and write enable can initiate and terminate write cycle. 30a097-32 rev. g 6
dense-pac microsystems, inc. dps128x16cn3/dps128x16bn3 write cycle 3: we controlled. oe is low. 8, 9 address ce we data in data out write cycle 2: we controlled. oe is high. 8, 9 address ce we data in data out 30a097-32 rev. g 7
dps128x16cn3/dps128x16bn3 dense-pac microsystems, inc. (48 - pin leadless stack) mechanical drawing (48 - pin straight leaded stack) mechanical drawing 30a097-32 rev. g 8
dense-pac microsystems, inc. dps128x16cn3/dps128x16bn3 (48 - pin ??j?? leaded stack) mechanical drawing (48 - pin gullwing leaded stack) mechanical drawing 30a097-32 rev. g 9
dps128x16cn3/dps128x16bn3 dense-pac microsystems, inc. ordering information dense-pac microsystems, inc. 7321 lincoln way garden grove , california 92841-1431 (714) 898-0007 (800) 642-4477 (outside ca) fax: (714) 897-1772 http://www.dense-pac.com (50 - pin pga) mechanical drawing 30a097-32 rev. g 10
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